The present invention relates generally to metal-oxide-semiconductor (MOS) field effect devices, and more particularly to an improved, ultra high speed complementary MOS structure adapted for large scale integration (LSI).
Integrated circuit technology has been characterized in recent years by a continued push for higher circuitry density to permit greater levels of integration. Most of the development activity has involved metal-oxide-semiconductor technology. With the growing use of large and very large scale integration, complementary metal-oxide-semiconductor (CMOS) circuits have experienced increased interest because of their extremely low "standby" power consumption and high noise immunity.
Complementary MOS devices combine p-channel and n-channel enhancement mode transistors on a common substrate, the basic circuit in CMOS logic being a complementary inverter (FIG. 2). One prior art technique for achieving greater circuit density is device scaling--simply reducing the dimensions of standard CMOS device. Scaling down the dimensions of a semiconductor device also increases its speed and reduces its power dissipation. Another known approach is to make the n-channel half of the complementary structure using one of the newer, high performance n-MOS technologies. For instance, a CMOS integrated circuit consisting of a double-diffused planar metal-oxide-semiconductor (DMOS) n-channel device and a standard metal gate p-channel device is described by Masuhara et al. in IEEE J. Solid-State Circuits, Vol. SC-11, No. 4, pp. 453-8 (August, 1976). In addition, certain high performance n-MOS processes have been adapted to the fabrication of complete CMOS devices. U.S. Pat. No. 3,821,776 to Hayashi et al. describes a complementary DMOS structure, for example, and U.S. Pat. No. 4,131,907 to Ouyang shows a complementary V-groove MOS device. A CMOS structure consisting of a p-channel DMOS transistor and an n-channel double-diffused VMOS transistor is the subject of a paper by Jhabvala et al. in IEEE Trans. Electron Devices, Vol. ED-25, No. 7, pp. 848-50 (July, 1978).
These prior art CMOS structures have certain drawbacks, however. For example, it is difficult to manufacture very high performance devices solely by scaling down conventional planar structures because of the need to form extremely fine patterns accurately and reproducibly. In addition, planar technologies require more substrate surface area than equivalent performance nonplanar MOS devices. The production of V-groove structures requires a special, high cost anisotropic etching process. And while vertical channel VMOS has a compact configuration, it has circuit limitations when used in LSI applications. Lateral channel VMOS devices, such as those used in Ouyang and Jhabvala et al. CMOS structures, have relatively long drift regions, increasing their source-to-drain resistance.
Accordingly, a principal object of the present invention is to provide a new, very high performance CMOS structure. A related object is to provide an improved complimentary MOS device that is free of the disadvantages associated with prior art CMOS structures.